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| Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller C164CI Data Sheet 02.98 Preliminary ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ C164CI Revision History: Previous Releases: Page 3, 4 25...30 32, 33 33, 34 33, 34 39, 40 49, 50 - - Subjects 1998-02 Preliminary 04.97 (Advance Information) Alternate functions for P5 added. Register Table updated. IP6H and IP6L removed. Supply current specification improved. Idle supply current specification IIDO improved. (Referring to Revision 11.97) ADC specification improved. Description for READY removed. "AC Characteristics Demultiplexed Bus" removed. "AC Characteristics External Bus Arbitration" removed. Controller Area Network (CAN): License of Robert Bosch GmbH Edition 1998-02 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C164CI 16-Bit Microcontroller q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q C164CI q q High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32/16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via On-Chip PLL or via Direct or Prescaled Clock Input Up to 4 MBytes Linear Address Space for Code and Data 2 KByte On-Chip Internal RAM (IRAM) 64 KByte On-Chip OTP (C164CI-8EM) or ROM (C164CI-8RM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed External Address/Data Bus Four optional Chip Select Signals CS0 - CS3 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes with Flexible Power Management 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 32 Interrupt sources 8-Channel 10-bit A/D Converter with 9.7 s Conversion Time (8.2 s min.) 8-Channel 16-bit General Purpose Capture/Compare Unit (CAPCOM2) Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel) Two Serial Channels (Synchronous/Asynchronous and High-Speed Synchronous) Multi-Functional General Purpose Timer Unit with three 16-bit Timers On-Chip Full-CAN Interface (V2.0B active) with 15 Message Objects and Basic CAN Feature Up to 59 General Purpose I/O Lines Programmable Watchdog Timer and Oscillator Watchdog On-Chip Real Time Clock Ambient temperature range -40 to 125 C Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 80-Pin MQFP Package, 0.65 mm pitch This document describes the SAF-C164CI-8EM and the SAK-C164CI-8EM. For simplicity all versions are referred to by the term C164CI throughout this document. Semiconductor Group 3 1998-02 C164CI Introduction The C164CI is a new low cost derivative of the Siemens C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip ROM or OTP and clock generation via PLL. The C164CI derivative is especially suited for cost sensitive applications. VDD VSS XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR PORT0 16 bit PORT1 16 bit Port 3 9 bit C164CI Port 4 6 bit Port 8 4 bit Port 5 8 bit VAREF Figure 1 Logic Symbol VAGND Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, ie. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C164CI please refer to the Product Information Microcontrollers", which summarizes all available microcontroller variants. q q q q Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 4 1998-02 C164CI Pin Configuration (top view) VAGND P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P8.3/CC19IO P8.2/CC18IO P8.1/CC17IO P8.0/CC16IO NMI RSTOUT RSTIN P1H.7/CC27IO P1H.6/CC26IO P1H.5/CC25IO P1H.4/CC24IO P1H.3/EX3IN/T7IN P1H.2/CC6POS2/EX2IN P1H.1/CC6POS1/EX1IN VDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VAREF P5.4/AN4/T2EUD P5.5/AN5/T4EUD P5.6/AN6/T2IN P5.7/AN7/T4IN VSS VDD P3.4/T3EUD P3.6/T3IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT P4.0/A16/CS3 P4.1/A17/CS2 P4.2/A18/CS1 VSS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C164CI Figure 2 Semiconductor Group VDD P4.3/A19/CS0 P4.5/A20/CAN_RxD P4.6/A21/CAN_TxD RD WR/WRL ALE VPP/EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P0H.0/AD8 P0H.1/AD9 P0H.2/AD10 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS P1H.0/CC6POS0/EX0IN P1L.7/CTRAP P1L.6/COUT63 VSS XTAL1 XTAL2 VDD P1L.5/COUT62 P1L.4/CC62 P1L.3/COUT61 P1L.2/CC61 P1L.1/COUT60 P1L.0/CC60 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 Vss 5 1998-02 C164CI Pin Definitions and Functions Symbol P5.0 - P5.7 Pin Input (I) Number Output (O) 76 - 79, 2-5 I I I Function Port 5 is a 8-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 8) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x). The following pins of Port 5 also serve as timer inputs: P5.4 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input P5.5 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.6 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P5.7 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture Port 3 is a 9-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 3 pins also serve for alternate functions: P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TXD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RXD0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE Ext. Memory High Byte Write Strobe WRH P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line Chip Select 3 Output CS3 ... ... ... P4.3 A19 Segment Address Line Chip Select 0 Output CS0 P4.5 A20 Segment Address Line, CAN_RxD CAN Receive Data Input P4.6 A21 Most Significant Segment Addr. Line, CAN_TxD CAN Transmit Data Output P3.4, P3.6, P3.8 - P3.13, P3.15 8, 9, 10 - 15, 16 8 9 10 11 12 13 14 15 16 I/O I/O I/O I/O I/O I I I/O I/O O I/O O I/O O I/O I/O I/O I/O P4.0 - P4.3 P4.5 - P4.6 17 - 19, 22, 23 24 17 ... 22 23 24 O O ... O O O I O O Semiconductor Group 6 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol RD WR / WRL Pin Input (I) Number Output (O) 25 26 O O Function External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C164CI to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. Note: This pin also accepts the programming voltage for OTP versions of the C164CI. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address and data (AD) bus. Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 ALE 27 O EA 28 I PORT0: P0L.0 - P0L.7, P0H.0 P0H.7 I/O 29 36 37 - 39, 42 - 46 Semiconductor Group 7 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol PORT1: P1L.0 - P1L.7, P1H.0 P1H.7 Pin Input (I) Number Output (O) I/O 47 - 52, 57 - 58 59, 62 - 68 47 48 49 50 51 52 57 58 Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 1 pins also serve for alternate functions: P1L.0 CC60 CAPCOM6: Input / Output of Ch. 0 P1L.1 COUT60 CAPCOM6: Output of Channel 0 P1L.2 CC61 CAPCOM6: Input / Output of Ch. 1 P1L.3 COUT61 CAPCOM6: Output of Channel 1 P1L.4 CC62 CAPCOM6: Input / Output of Ch. 2 P1L.5 COUT62 CAPCOM6: Output of Channel 2 P1L.6 COUT63 Output of 10-bit Compare Channel CAPCOM6: Trap Input P1L.7 CTRAP CTRAP is an input pin with an internal pullup resistor. A low level on this pin switches the compare outputs of the CAPCOM6 unit to the logic level defined by software. CAPCOM6: Position 0 Input P1H.0 CC6POS0 EX0IN Fast External Interrupt 0 Input CAPCOM6: Position 1 Input P1H.1 CC6POS1 EX1IN Fast External Interrupt 1 Input CAPCOM6: Position 2 Input P1H.2 CC6POS2 EX2IN Fast External Interrupt 2 Input P1H.3 EX3IN Fast External Interrupt 3 Input T7IN CAPCOM2: Timer T7 Count Input P1H.4 CC24IO CAPCOM2: CC24 Capture Input ... ... ... P1H.7 CC27IO CAPCOM2: CC27 Capture Input Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C164CI. An internal pullup resistor permits poweron reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is pulled low for the duration of the internal reset sequence upon a software or WDT reset. 1) XTAL1: I/O O I/O O I/O O O I 59 62 63 64 65 ... 68 XTAL1 XTAL2 55 54 I I I I I I I I I ... I I O RSTIN 69 I Semiconductor Group 8 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Number Output (O) O Function Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C164CI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Port 8 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.3 CC19IO CAPCOM2: CC19 Cap.-In/Comp.Out Reference voltage for the A/D converter. Reference ground for the A/D converter. Digital Supply Voltage: + 3 V / + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground. RSTOUT 70 NMI 71 I P8.0 - P8.3 72 75 I/O I/O 72 ... 75 I/O ... I/O - VAREF VAGND VDD 1 80 7, 21, 40, 53, 61 6, 20, 41, 56, 60 VSS - 1) The following behaviour differences must be observed when the bidirectional reset is active: Bit BDRSTEN in register SYSCON cannot be changed after EINIT. After a reset bit BDRSTEN is cleared. Bit WDTR will always be '0', even after a watchdog timer reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. q Pin RSTIN may only be connected to external reset devices with an open drain output driver. q q q q Semiconductor Group 9 1998-02 C164CI Functional Description The C164CI is a low cost downgrade of the high performance microcontroller C167CR with OTP or internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with an additional functionality. The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164CI. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). 64K Internal ROM (C164CI-8RM) or OTP (C164CI-8EM) 32 Instr./Data 16 Data Dual Port 16 C166-Core CPU Core CPU Data 16 16 Internal RAM 2 KByte PLL-Oscillator XTAL progr. Multiplier: 0.5; 1; 1.5; 2; 2.5; 3; 4; 5 External Instr./Data PEC up to 12 ext. IR RTC WDT XBUS (16-bit NON MUX Data / Addresses) P4.5/CAN_RxD P4.6/CAN_TxD Full-CAN Interface V2.0B active 16 Interrupt Controller Peripheral Data Interrupt Bus 16 16 Port 0 External Bus (8/16 bit; MUX only) & XBUS Control ASC BRG SSC BRG T3 T4 Timer 7 Timer 8 T2 Timer 13 8Channel 10-Bit ADC USART Sync. Channel (SPI) GPT 1 General Purpose Capture/Compare Unit Capture/Compare Unit for PWM Generation (CAPCOM6) 8-Channel 16-bit Capture/Compare Unit (CAPCOM2) 1 Compare Channel 3/6 Capture/Compare Channels 5 Port 4 Port 5 8 Port 3 9 Port 8 4 Port 1 C164CI V1.2 Figure 3 Block Diagram Semiconductor Group 10 1998-02 C164CI Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C164CI incorporates 64 KByte of on-chip ROM or OTP memory for code or constant data. The OTP memory can be programmed by the CPU itself (in system, eg. during booting) or directly via an external interface (eg. before assembly). The programming time is approx. 100 sec per word. An external programming voltage VPP = 11.5 V must be supplied for this purpose (via pin EA). 2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C16x family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of two different external memory access modes, which are as follows: - 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. For applications which require less than 4 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used. Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface pins. Semiconductor Group 11 1998-02 C164CI Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C164CI's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Registers 16 Internal RAM R15 General Purpose R15 R0 16 MCB02147 Figure 4 CPU Block Diagram Semiconductor Group 12 1998-02 C164CI The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C164CI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 13 1998-02 C164CI Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the C164CI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C164CI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or PEC Service Request Fast External Interrupt 0 Fast External Interrupt 1 Fast External Interrupt 2 Fast External Interrupt 3 GPT1 Timer 2 GPT1 Timer 3 Request Flag CC8IR CC9IR CC10IE CC11IE T2IR T3IR Enable Flag CC8IE CC9IE CC10IE CC11IE T2IE T3IE Interrupt Vector CC8INT CC9INT CC10INT CC11INT T2INT T3INT Vector Location 00'0060 H 00'0064H 00'0068H 00'006CH 00'0088H 00'008CH Trap Number 18H 19H 1AH 1BH 22H 23H Semiconductor Group 14 1998-02 C164CI Source of Interrupt or PEC Service Request GPT1 Timer 4 A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Timer 7 CAPCOM Timer 8 CAPCOM 6 Interrupt XPER Node 0 Int / CAN ASC0 Transmit Buffer CAPCOM 6 Timer 12 CAPCOM 6 Timer 13 CAPCOM 6 Emergency Request Flag T4IR ADCIR ADEIR S0TIR S0RIR S0EIR SCTIR SCRIR SCEIR CC16IR CC17IR CC18IR CC19IR CC24IR CC25IR CC26IR CC27IR T7IR T8IR CC6IR XP0IR S0TBIR T12IR T13IR CC6EIR Enable Flag T4IE ADCIE ADEIE S0TIE S0RIE S0EIE SCTIE SCRIE SCEIE CC16IE CC17IE CC18IE CC19IE CC24IE CC25IE CC26IE CC27IE T7IE T8IE CC6IE XP0IE XP3IE S0TBIE T12IE T13IE CC6EIE Interrupt Vector T4INT ADCINT ADEINT S0TINT S0RINT S0EINT SCTINT SCRINT SCEINT CC16INT CC17INT CC18INT CC19INT CC24INT CC25INT CC426NT CC27INT T7INT T8INT CC6INT XP0INT XP3INT S0TBINT T12INT T13INT CC6EINT Vector Location 00'0090H 00'00A0 00'00A4 00'00A8H 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'00C0H 00'00C4H 00'00C8H 00'00CCH 00'00E0H 00'00E4H 00'00E8H 00'00ECH 00'00F4H 00'00F8H 00'00FCH 00'0100H 00'010CH 00'011CH 00'0134H 00'0138H 00'013CH Trap Number 24H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 38H 39H 3AH 3BH 3DH 3EH 3FH 40H 43H 47H 4DH 4EH 4FH XPER Node 3 Int / PLL / T14 XP3IR Semiconductor Group 15 1998-02 C164CI The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET Vector Location 00'0000H 00'0000H 00'0000H Trap Number 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH Trap Priority III III III II II II I I I I I NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H [2CH - 3CH] [0BH - 0FH] Any [00'0000H - 00'01FCH] in steps of 4H Any [00H - 7FH] Current CPU Priority Semiconductor Group 16 1998-02 C164CI The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 400 ns (at 20 MHz system clock). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/ compare register array. Each dual purpose capture/compare register, which may be individually allocated to either CAPCOM timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Registers CC16 & CC24 (c) pin CC16IO Registers CC17 & CC25 (c) pin CC17IO Registers CC18 & CC26 (c) pin CC18IO Registers CC19 & CC27 (c) pin CC19IO Semiconductor Group 17 1998-02 C164CI The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM output signal and is further used to modulate the capture/compare output signals. In capture mode the contents of compare timer 12 is stored in the capture registers upon a signal transition at pins CCx. For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). Compare timers 12 (16-bit) and 13 (10-bit) are free running timers which are clocked by the prescaled CPU clock. Period Register T12P Mode Select Register CC6MSEL CC Channel 0 CC60 Control CC Channel 1 CC61 CC Channel 2 CC62 Trap Register CTRAP Prescaler Offset Register T12OF Compare Timer T12 16-Bit 1) Port Control Logic CC60 COUT60 CC61 COUT61 CC62 COUT62 f CPU Control Register CTCON Prescaler f CPU Compare Timer T13 10-Bit 1) Compare Register CMP13 Block Commutation Control CC6M CON.H COUT63 CC6POS0 CC6POS1 CC6POS2 Period Register T13P 1) These Registers are not direct accessable. The period and offset registers are loading a value into the timer registers. MCB03700 Figure 5 CAPCOM6 Block Diagram Semiconductor Group 18 1998-02 C164CI General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers. Each timer may operate independently in a number of different modes, or may be concatenated with another timer. Timer T3 can be configured for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. Timers T2 and T4 can only be operated in timer mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes the associated port pin (T3IN) serves as gate or clock input. The maximum resolution of the timers is 400 ns (@ 20 MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on pin T3EUD for T3 to facilitate eg. position tracking. In Incremental Interface Mode timer T3 can be directly connected to the incremental position sensor signals A and B via the respective inputs T3IN and T3EUD. Direction and count signals are internally derived from these two input signals, so the contents of timer T3 corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload registers for timer T3. When used as reload registers, timers T2 and T4 are stopped. Timer T3 is reloaded with the contents of T2 or T4 triggered by a selectable state transition of its toggle latch T3OTL. Semiconductor Group 19 1998-02 C164CI X Figure 6 GPT Block Diagram Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz). Semiconductor Group 20 1998-02 C164CI Real Time Clock The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks, a fixed 8bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver and is therefore independent from the selected clock generation mode of the C164CI. All timers count up. The RTC module can be used for different purposes: q System clock to determine the current time and date q Cyclic time based interrupt q 48-bit timer for long term measurements T14REL Reload T14 8:1 fRTC Interrupt Request RTCL RTCL Figure 6-1 RTC Block Diagram Note: The register associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed. Semiconductor Group 21 1998-02 C164CI A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C164CI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (eg. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. Semiconductor Group 22 1998-02 C164CI Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 625 KBaud and half-duplex synchronous communication at up to 2.5 MBaud @ 20 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 5 Mbaud @ 20 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Semiconductor Group 23 1998-02 C164CI CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), ie. the on-chip CANModule can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins of Port 4 to interface to a bus transceiver. Note: When the CAN interface is to be used the segment address output on Port 4 must be limited to 4 bits, ie. A19...A16. This is necessary to enable the alternate function of the CAN interface pins. Parallel Ports The C164CI provides up to 59 IO lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of two IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Ports P1L, P1H and P8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or serve as external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Semiconductor Group 24 1998-02 C164CI Instruction Set Summary The table below lists the instructions of the C164CI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C16x Family Instruction Set Manual". This document also provides a detailled description of each instruction. Instruction Set Summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 Semiconductor Group 25 1998-02 C164CI Instruction Set Summary (cont'd) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack und update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2 Semiconductor Group 26 1998-02 C164CI Special Function Registers Overview The following table lists all SFRs which are implemented in the C164CI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Name ADCIC ADCON ADEIC ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 Physical 8-Bit Address Address b FF98H b FFA0H b FF9AH FEA0H FE18H FE1AH FE1CH FE1EH CCH D0H CDH 50H 0CH 0DH 0EH 0FH 86H 8AH 8BH 8CH 8DH Description A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Overrun Error Interrupt Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 CAN Bit Timing Register CAN Control / Status Register CAN Global Mask Short CAN Interrupt Register CAN Lower Global Mask Long CAN Lower Mask of Last Message CAN Upper Global Mask Long CAN Upper Mask of Last Message CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 Interrupt Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H UUUUH XX01H UFUUH XXH UUUUH UUUUH UUUUH UUUUH 0000H 0000H F0A0H E 50H BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH C1BTR C1CSR C1GMS C1IR C1LGML C1LMLM C1UGML C1UMLM CC10IC CC11IC EF04H X --EF00H X --EF06H X --EF02H X --EF0AH X --EF0EH X --EF08H X --EF0CH X --b FF8CH b FF8EH C6H C7H Semiconductor Group 27 1998-02 C164CI Name CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC60 CC61 CC62 CC6EIC CC6IC CC6MIC CC6MSEL CC8IC CC9IC CCM4 CCM6 CMP13 CP CSP CTCON Physical 8-Bit Address Address FE60H FE62H FE64H FE66H FE70H FE72H FE74H FE76H FE30H FE32H FE34H 30H 31H 32H 33H 38H 39H 3AH 3BH 18H 19H 1AH b F160H E B0H b F162H E B1H b F164H E B2H b F166H E B3H b F170H E B8H b F172H E B9H b F174H E BAH b F176H E BBH Description CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM 6 Register 0 CAPCOM 6 Register 1 CAPCOM 6 Register 2 CAPCOM 6 Emergency Interrupt Control Reg. CAPCOM 6 Interrupt Control Register CAPCOM 6 Mode Control Register CAPCOM 6 Mode Interrupt Control Register CAPCOM 6 Mode Select Register CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 Interrupt Control Register CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 6 CAPCOM 6 Timer 13 Compare Register CPU Context Pointer Register CPU Code Segment Pointer Register (8 bits, not directly writeable) CAPCOM 6 Compare Timer Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00FFH 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H 0000H 1010H b F188H E C4H b F17EH E BFH 99H 9BH C4H C5H 91H 93H 1BH 08H 04H 98H b FF36H b FF88H b FF8AH b FF22H b FF26H FE36H FE10H FE08H b FF30H CC6MCON b FF32H F036H E 1BH Semiconductor Group 28 1998-02 C164CI Name DP0H DP0L DP1H DP1L DP3 DP4 DP8 DPP0 DPP1 DPP2 DPP3 EXICON EXISEL IDCHIP IDMANUF IDMEM IDPROG ISNC LAR MCFG MCR MDC MDH MDL ODP3 ODP8 ONES OPAD OPCTRL OPDAT P0H P0L P1H Physical 8-Bit Address Address b F102H E 81H b F100H E 80H b F106H E 83H b F104H E 82H b FFC6H b FFCAH b FFD6H FE00H FE02H FE04H FE06H E3H E5H EBH 00H 01H 02H 03H Description P0H Direction Control Register P0L Direction Control Register P1H Direction Control Register P1L Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register External Interrupt Source Select Register Identifier Identifier Identifier Identifier Interrupt Subnode Control Register CAN Lower Arbitration Register (msg. n) CAN Message Configuration Register (msg. n) CAN Message Control Register (msg. n) CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 3 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) OTP Programming Interface Address Register OTP Programming Interface Control Register OTP Programming Interface Data Register Port 0 High Register (Upper half of PORT0) Port 0 Low Register (Lower half of PORT0) Port 1 High Register (Upper half of PORT1) Reset Value 00H 00H 00H 00H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0A01H 1820H X010H XXXXH 0000H UUUUH UUH UUUUH 0000H 0000H 0000H 0000H 00H FFFFH 0000H 0007H 0000H 00H 00H 00H b F1C0H E E0H b F1DAH E EDH F07CH E 3EH F07EH E 3FH F07AH E 3DH F078H E 3CH b F1DEH E EFH EFn4H X --EFn6H X --EFn0H X --b FF0EH FE0CH FE0EH 87H 06H 07H b F1C6H E E3H b F1D6H E EBH b FF1EH 8FH EDC2H X --EDC0H X --EDC4H X --b FF02H b FF00H b FF06H 81H 80H 83H Semiconductor Group 29 1998-02 C164CI Name P1L P3 P4 P5 P5DIDIS P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PSW RP0H RTCH RTCL S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR Physical 8-Bit Address Address b FF04H b FFC4H b FFC8H b FFA2H b FFA4H b FFD4H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H 82H E2H E4H D1H D2H EAH 60H 61H 62H 63H 64H 65H 66H 67H 88H Description Port 1 Low Register (Lower half of PORT1) Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 5 Digital Input Disable Register Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register CPU Program Status Word System Startup Configuration Register (Rd. only) RTC High Register RTC Low Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register Reset Value 00H 0000H 00H XXXXH 0000H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH XXXXH XXXXH 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H FC00H 0000H b F1C4H E E2H b F108H E 84H F0D6H E 6BH F0D4H E 6AH FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H b F19CH E CEH FEB0H b FF6CH FE12H 58H B6H 09H F0B4H E 5AH Semiconductor Group 30 1998-02 C164CI Name SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON Physical 8-Bit Address Address b FFB2H b FF76H b FF74H b FF72H FE14H FE16H b FF12H D9H BBH BAH B9H 0AH 0BH 89H Description SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CPU System Configuration Register 2 CPU System Configuration Register 3 CAPCOM 6 Timer 12 Interrupt Control Register CAPCOM 6 Timer 12 Offset Register CAPCOM 6 Timer 12 Period Register CAPCOM 6 Timer 13 Interrupt Control Register CAPCOM 6 Timer 13 Period Register RTC Timer 14 Register RTC Timer 14 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register Reset Value 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0XX0H1) 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXXXH XXXXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H F0B2H E 59H F0B0H E 58H SYSCON2 b F1D0H E E8H SYSCON3 b F1D4H E EAH T12IC T12OF T12P T13IC T13P T14 T14REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T7 T78CON T7IC T7REL T8 T8IC b F190H E C8H F034H E 1AH F030H E 18H b F198H E CCH F032H E 19H F0D2H E 69H F0D0H E 68H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H b FF20H 20H A0H B0H 21H A1H B1H 22H A2H B2H 90H F050H E 28H b F17AH E BDH F054H E 2AH F052H E 29H b F17CH E BEH Semiconductor Group 31 1998-02 C164CI Name T8REL TFR TRCON UAR WDT XP0IC XP3IC ZEROS 1) 2) Physical 8-Bit Address Address F056H E 2BH b FFACH b FF34H FEAEH D6H 9AH 57H D7H Description CAPCOM Timer 8 Reload Register Trap Flag Register CAPCOM 6 Trap Enable Control Register CAN Upper Arbitration Register (msg. n) Watchdog Timer Register (read only) Watchdog Timer Control Register X-Peripheral 0 Interrupt Control Register X-Peripheral 3 Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H 00XXH UUUUH 0000H 00XXH2) 0000H 0000H 0000H EFn2H X --- WDTCON b FFAEH b F186H E C3H b F19EH E CFH b FF1CH 8EH The system configuration is selected during reset. The reset value depends on the indicated reset source. Semiconductor Group 32 1998-02 C164CI Absolute Maximum Ratings Ambient temperature under bias (TA): SAF-C164CI ................................................................................................................ -40 to +85 C SAK-C164CI .............................................................................................................. -40 to +125 C Storage temperature (TST)........................................................................................ - 65 to +150 C Voltage on VDD pins with respect to ground (VSS) ..................................................... -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) .................................................-0.5 to VDD +0.5 V Input current on any pin during overload condition.................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDD or VIN Semiconductor Group 33 1998-02 C164CI DC Characteristics VDD = 4.25 - 5.5 V; VSS = 0 V; fCPU = 20 MHz TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI Parameter Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Symbol min. Limit Values max. 0.2 VDD - 0.1 2.0 V V V V V V mV V - - - - - - - Unit Test Condition VIL SR - 0.5 VILS SR - 0.5 VIH SR 0.2 VDD + 0.9 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 VIH1 SR 0.6 VDD VIH2 SR 0.7 VDD VIHS SR 0.8 VDD - 0.2 HYS 400 Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) IOL = 2.4 mA VOL1 CC - 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0.45V Output high voltage VOH CC 0.9 VDD (PORT0, PORT1, Port 4, ALE, RD, 2.4 WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) 1) VOH1 CC 0.9 VDD 2.4 - 200 500 5 250 -40 - 40 - -10 - V V nA nA mA k A A A A A A Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current ALE active current 4) 4) 4) 4) 4) IOZ1 CC - IOZ2 CC - IOV IRWH IRWL IALEL IALEH IP0H IP0L SR - 2) 3) 2) 3) 2) 3) RRST CC 50 - -500 - 500 - -100 - VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VIN = VIHmin VIN = VILmax PORT0 configuration current Semiconductor Group 34 1998-02 C164CI Parameter XTAL1 input current Pin capacitance (digital inputs/outputs) Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Power-down mode supply current with RTC running Power-down mode supply current with RTC disabled 5) Symbol min. Limit Values max. 20 10 10 + 3.5 x fCPU 5+ 1.25 x fCPU Unit A pF mA mA Test Condition 0 V < VIN < VDD IIL CC - CIO CC - IDD IIDX IIDO - - - f = 1 MHz TA = 25 C RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) 500 + A 9) 50 x fOSC 100 + A 25 x fOSC 9) 50 A IPDR IPDO - - VDD = 5.5 V fOSC in [MHz] 7) VDD = 5.5 V 7) Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Adapt-mode. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. A typical value for IPDR at room temperature and fOSC = 16 MHz is 300 A. 2) 3) 4) 5) 6) 7) 8) 9) Semiconductor Group 35 1998-02 C164CI I [mA] IDDmax 80 IDDtyp 40 IIDXmax IIDXtyp 10 5 10 15 20 fCPU [MHz] Figure 7 Active and Idle Supply Current as a Function of Operating Frequency I [A] 1500 1250 1000 IIDOtyp 750 500 250 IPDOmax 4 8 12 16 fOSC [MHz] IPDRmax IIDOmax Figure 8 Idle and Power Down Supply Current as a Function of Oscillator Frequency Semiconductor Group 36 1998-02 C164CI AC Characteristics Definition of Internal Timing The internal operation of the C164CI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). Phase Locked Loop Operation fXTAL fCPU TCL TCL Direct Clock Drive fXTAL fCPU TCL TCL Prescaler Operation fXTAL fCPU TCL TCL Figure 9 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate f CPU. This influence must be regarded when calculating the timings for the C164CI. Note: The example for PLL operation shown in the figure above refers to a PLL factor of 4. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). The table below associates the combinations of these three bits with the respective clock generation mode. Semiconductor Group 37 1998-02 C164CI C164CI Clock Generation Modes P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1) 2) CPU Frequency fCPU = fXTAL * F External Clock Input Notes Range 1) 2.5 to 5 MHz 3.33 to 6.66 MHz 5 to 10 MHz 2 to 4 MHz 1 to 20 MHz 6.66 to 13.3 MHz 2 to 40 MHz 4 to 8 MHz CPU clock via prescaler Direct drive 2) Default configuration 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXTAL * 4 fXTAL * 3 fXTAL * 2 fXTAL * 5 fXTAL * 1 fXTAL * 1.5 fXTAL / 2 fXTAL * 2.5 The external clock input range refers to a CPU clock range of 10...20 MHz. The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When pins P0.15-13 (P0H.7-5) equal '001' during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the period of the input clock f XTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the duty cycle of the input clock f XTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL * DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t 11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin. Semiconductor Group 38 1998-02 C164CI Phase Locked Loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (ie. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: TCLmin = TCLNOM * (1 - DN / 100) DN = (4 - N /15) [%], where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (ie. N = 3): D3 = 4 - 3/15 = 3.8%, and (3TCL)min = 3TCLNOM * (1 - 3.8 / 100) = 3TCLNOM * 0.962 (57.72 nsec @ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Max.jitter [%] This approximated formula is valid for 1 N 40 and 10MHz fCPU 25MHz. 4 3 2 1 8 2 4 16 32 N Figure 10 Approximated Maximum PLL Jitter Semiconductor Group 39 1998-02 C164CI AC Characteristics External Clock Drive XTAL1 VDD = 4.25 - 5.5 V; TA = -40 to +85 C TA = -40 to +125 C Parameter Oscillator period High time Low time Rise time Fall time 1) 2) VSS = 0 V for SAF-C164CI for SAK-C164CI Symbol Direct Drive 1:1 min. max. 8000 - - 10 2) 2) Prescaler 2:1 min. 25 6 6 - - max. 4000 - - 6 2) PLL 1:N min. 75 1) 10 10 - - max. 500 1) - - 10 2) Unit ns ns ns ns ns tOSC SR 50 t1 t2 t3 t4 SR 18 2) SR 18 SR - SR - 10 2) 6 2) 10 2) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. The clock input signal must reach the defined levels VIL and VIH2. t1 0.5 VCC t3 t4 VIH2 VIL te t asc MCT02534 Figure 11 External Clock Drive XTAL1 Semiconductor Group 40 1998-02 C164CI A/D Converter Characteristics VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI 4.0 V VAREF VDD+0.1 V ; VSS-0.1 V VAGND VSS+0.2 V Parameter Analog input voltage range Basic clock frequency Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol Limit Values min. max. Unit V MHz Test Condition 1) 2) 3) VAIN SR VAGND fBC tC 0.5 CC - VAREF 6 40 tBC + tS + 2 tCPU 2 tCPU = 1 / fCPU LSB k k pF 4) TUE CC - RAREF SR - RASRC SR - CAIN CC - tBC / 60 - 0.25 tBC in [ns] 5) 6) tS in [ns] 6) 7) 6) tS / 450 - 0.25 33 Sample time and conversion time of the C164CI's A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. ADCON.15|14 A/D Converter Basic clock (ADCTC) fBC 2) 00 01 10 11 fCPU / 4 fCPU / 2 fCPU / 16 fCPU / 8 ADCON.13|12 Sample time tS 7) (ADSTC) 00 01 10 11 tBC * 8 tBC * 16 tBC * 32 tBC * 64 Converter Timing Example: Assumptions: fCPU = 20 MHz (ie. tCPU = 50 ns), ADCTC = '00', ADSTC = '00'. = fCPU / 4 = 5 MHz, ie. tBC = 200 ns. = tBC * 8 = 1600 ns. = tS + 40 tBC + 2 tCPU = (1600 + 8000 + 100) ns = 9.7 s. Basic clock fBC Sample time tS Conversion time tC Semiconductor Group 41 1998-02 C164CI Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, guaranteed by design. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from the table above. 2) 3) 4) 5) 6) 7) Semiconductor Group 42 1998-02 C164CI Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 12 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 13 Float Waveforms Semiconductor Group 43 1998-02 C164CI Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values tA tC tF TCL * AC Characteristics Multiplexed Bus VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) max. - - - - - 6 31 - - 30 + tC 15 + tA 9 + tA 15 + tA 15 + tA -10 + tA - - 40 + tC 65 + tC - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 16 + tA - TCL - 10 + tA - TCL - 10 + tA - -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - 6 TCL + 6 - - 2TCL - 20 + tC Unit t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 CC CC CC CC CC CC CC CC CC SR Semiconductor Group 44 1998-02 C164CI Parameter Symbol Max. CPU Clock = 20 MHz min. max. 55 + tC 55 + tA + tC 70 + 2tA + tC - 36 + tF - - - - 10 - tA 55 + tC + 2tA - - - 0 25 26 + tC 51 + tC - - - 0 - 30 + tC 36 + tF 36 + tF 36 + tF -4 - tA - 61 + tF 21 + tA -4 + tA - - - - - - - 0 - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC Unit RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) t15 t16 t17 t18 t19 t22 t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46 t47 SR SR SR SR SR CC CC CC CC CC SR CC CC CC CC CC SR SR ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA - 3TCL - 14 + tF TCL - 4 + tA -4 + tA - - - - Semiconductor Group 45 1998-02 C164CI Parameter Symbol Max. CPU Clock = 20 MHz min. max. - - - - 30 + tF - - 40 + tC 65 + tC 36 + tC 0 - 30 + tF 30 + tF Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - - - - 2TCL - 20 + tF - - Unit RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS t48 t49 t50 t51 t52 t54 t56 CC CC CC SR SR CC CC ns ns ns ns ns ns ns Semiconductor Group 46 1998-02 C164CI t5 ALE t16 t25 t38 CSx t39 t40 A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS t7 t18 Address Data In t54 t19 t8 RD t10 t14 t44 t12 t46 t48 t51 t52 t42 RdCSx Write Cycle BUS Address t23 Data Out t8 WR, WRL, WRH t10 t56 t22 t12 t50 t48 t42 WrCSx t44 Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 47 1998-02 C164CI t5 ALE t16 t38 t39 t25 t40 CSx A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS Address t7 t18 Data In t54 t19 t8 RD t10 t14 t44 t12 t46 t48 t51 t52 t42 RdCSx Write Cycle BUS Address Data Out t23 t8 WR, WRL, WRH t10 t56 t22 t12 t50 t48 t42 WrCSx t44 Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 48 1998-02 C164CI t5 ALE t16 t25 t38 CSx t39 t40 A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS t7 t18 Address Data In t54 t19 t9 RD t11 t15 t13 t51 t52 t43 RdCSx t45 t47 t49 Write Cycle BUS Address t23 Data Out t9 WR, WRL, WRH t56 t11 t22 t13 t45 t50 t49 t43 WrCSx Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 49 1998-02 C164CI t5 ALE t16 t38 t39 t25 t40 CSx A23-A16 (A15-A8) BHE t17 Address t27 t6 Read Cycle BUS Address t7 t18 Data In t54 t19 t9 RD t11 t15 t13 t51 t52 t43 RdCSx t45 t47 t49 Write Cycle BUS Address Data Out t23 t56 t9 WR, WRL, WRH t11 t13 t22 t43 WrCSx t45 t49 t50 Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 50 1998-02 C164CI AC Characteristics CLKOUT VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge max. 50 - - 4 4 10 + tA 50 19 15 - - 0 + tA Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 6 TCL - 10 - - 0 + tA max. 2TCL - - 4 4 10 + tA ns ns ns ns ns ns Unit t29 t30 t31 t32 t33 t34 CC CC CC CC CC CC Semiconductor Group 51 1998-02 C164CI Running cycle 1) MUX/Tristate 3) t32 CLKOUT t33 t30 t34 t31 t29 4) ALE Command RD, WR 2) Figure 15 CLKOUT Timing Notes 1) 2) 3) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles. The next external bus cycle may start here. 4) Semiconductor Group 52 1998-02 C164CI Package Outline Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.25 min 2 +0.1 -0.05 2.45 max 0.65 0.3 0.08 0.88 C 12.35 17.2 14 1) 0.1 0.12 M A-B D C 80x 0.2 A-B D 80x 0.2 A-B D H 4x D A B 14 1) 17.2 80 1 Index Marking 0.6x45 1) Does not include plastic or metal protrusions of 0.25 max per side Figure 16 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 53 Dimensions in mm 1998-02 7max H 0.15 +0.08 -0.02 |
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